1. Field of the Invention
The embodiments disclosed herein relate to integrated circuit design and, more particularly, to a method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence.
2. Description of the Related Art
In integrated circuit design, statistical static timing analysis (SSTA) can be used to predict the performance of an integrated circuit and verify that the integrated circuit will function correctly. Specifically, SSTA can be used to predict the arrival times of clock and data signals and the results can be compared against established timing constraints (i.e., timing requirements) to see if the integrated circuit, as designed, will function properly with a sufficiently high probability.
For example, in an integrated circuit, a circuit block (e.g., latch, flip-flop, clock gating block, register, static memory, dynamic memory, etc.) will typically have both a setup time margin and a hold time margin for capturing a data signal input. The setup time margin is a specific period of time immediately prior to the arrival of an active edge of a clock signal input during which the data signal input must be stable for the circuit block to function properly, whereas the hold time margin is a specific period of time immediately after the arrival of the active edge of the clock signal input during which the data signal input must continue to remain stable for the circuit block to function properly. In other words, for such a circuit block to function properly the actual setup time must be greater than the setup time margin and the actual hold time must be greater than the hold time margin. To ensure that this happens, setup and hold time constraints (i.e., timing requirements) are established for each circuit block within a circuit. During integrated circuit design, a statistical static timing analysis (SSTA) is typically performed to predict the setup time and hold time for each circuit block. Then, the results are compared to the established time constraints to determine if a violation will occur or not. Specifically, timing slack is computed and this timing slack is indicative of the degree to which a particular time constraint (i.e., a setup time constraint or a hold time constraint) is violated (i.e., negative slack) or not violated (i.e., positive slack). Thus, negative slack indicates how much the setup time or the hold time must be improved by design to avoid violating the particular time constraint, whereas positive slack indicates how much the setup time or hold time can be made worse by design (e.g., to save cost, power, etc.) without violating the particular time constraint.
Currently used techniques for establishing the time constraints (i.e., the timing requirements) for a circuit block, which requires the checking of setup and hold timing constraints, are conservative in order to ensure that the circuit block will function properly and, thereby, avoid circuit failure. However, because such techniques generally do not consider the interdependence between the setup time margin and the hold time margin of the circuit block and do not consider the impact of the range of possible variations in process, environmental or other parameters that can affect circuit performance (i.e., do not involve parameterized SSTA), the techniques have to impose sufficient additional pessimism to ensure that for all combinations of setup and hold time values and for all combinations of process and environmental parameters the circuit block will function properly. Therefore, there is a need in the art for a technique that can be used to establish more optimistic time constraints (i.e., less pessimistic time constraints) for a circuit block (e.g., latch, flip-flop, clock gating block, register, static memory, dynamic memory, etc., which requires checking of setup and hold timing constraints) by considering the interdependence between the setup time margin and the hold time margin of the circuit block as well as the impact on the circuit block of variations in process, environmental or other parameters affecting circuit performance.